1. Field of the Invention
This invention relates to a semiconductor device, and more specifically to a chip scale package for use in packaging a central-pad die and a manufacturing method thereof.
2. Description of the Related Art
FIG. 1 depicts a conventional chip scale package 100 comprising an elastomer pad 110 with a slot 110a centrally defined therein interposed between a substrate 120 and a semiconductor chip 130. One purpose of the elastomer pad 110 is to obtain suitable reliability by minimizing CTE mismatch stress between the substrate 120 and the semiconductor chip 130.
The semiconductor chip 130 has a plurality of bonding pads 132 disposed centrally thereon. The substrate 120 includes a plurality of solder pads 122 and leads 124 provided on the upper surface thereof. The solder pads 122 are electrically connected to the corresponding leads 124 through conductive traces on the substrate 120. The substrate 120 has a plurality of through-holes respectively corresponding to the solder pads 122 such that each of the solder pads 122 has at least a portion exposed from its corresponding through-hole for mounting a solder ball 126. The substrate 120 has a slot 120a corresponding to the slot 110a of the elastomer pad 110 (see FIG. 2). The leads 124 are bonded to their corresponding bonding pads 132 of the semiconductor chip 130 for electrically connecting the semiconductor chip 130 to the substrate 120.
The encapsulation process of the chip scale package 100 typically comprises the steps of: (a) dispensing encapsulant into the slot 120a of the substrate 120 (see FIG. 3) to seal the leads 124, and then curing the encapsulant by baking to form the package body 140; and (b) flipping the product of step (a) over, then dispensing another encapsulant around the semiconductor chip 130 (see FIG. 4), and curing the encapsulant by baking to form the package body 150.
Since the encapsulation process of the chip scale package 100 must be carried out by repeating the steps of dispensing and curing twice, the encapsulation cycle time is prolonged. Therefore, the cost and cycle time for packaging a semiconductor chip is increased. Moreover, since the slot 120a of the substrate 120 is rather narrow, it is very difficult for dispensing the encapsulant into it. The encapsulant must be dispensed in precise amount and with proper flow, or it is easy to form flash on the substrate surface around the slot 120a, which in turn may contaminate the solder pads.